1. Field of the Invention
The present invention relates to a clock control circuit, and more particularly to a circuit for suppressing a clock pulse.
A data processing system consists usually of a plurality of logic modules or large-scale integrated circuits (LSI's) (hereinafter called "devices") which are located apart from each other and interchange data to perform data processing. The devices operate in synchronization with each other by means of the same system clock pulse to transfer a unit of data between the devices within a predetermined time, or a predetermined number of clock cycles. However, if a particular condition occurs in which data cannot be transferred within the predetermined time, the clock pulse has to be suppressed to wait for the data to be transferred (hereinafter such condition is called a "clock suppress condition").
Since a memory cycle and, therefore, a clock cycle must be set to accommodate the longest time possible required by the suppress conditions, the time required to transfer data is increased. This reduces the processing speed of a data processing system. Therefore, a clock control circuit which does not reduce system performance in this manner is in great demand.
2. Description of the Related Art
The related art is described taking a computer system with buffer memory (or cache memory) as an example.
FIG. 1 is a block diagram of a computer system for practicing the present invention. FIG. 2 is a circuit showing the first related art. FIG. 3 is a timing chart showing the occurrence of a cache hit to the circuit of FIG. 2. FIG. 4 is a timing chart showing the occurrence of a suppress condition to the circuit of FIG. 2. FIG. 5 is a circuit showing second related art. FIG. 6 is a timing chart showing the occurrence of a cache hit to the circuit of FIG. 5. FIG. 7 is a timing chart showing the occurrence of a clock suppress condition to the circuit of FIG. 5.
In FIG. 1, a memory access controller 11 generates a clock suppress signal or clock suppress request signal (CLKSP/CLKSPRQ), and sends the signal to all the devices, including itself, to perform a clock suppression. A processor unit CPU 12 accesses a buffer memory 13, registers 16 and a main memory 15, and performs arithmetic and logical operations. The buffer memory 13 tries to access the addressed data thereof and, when the addressed data is not found, activates a MISS-HIT signal. A clock generator 14 generates a system clock pulse CLK1 and distributes it to all the devices. A bus 6 carries data, address, access mode and other control signals among the memory access controller 11, CPU 12 and buffer memory 13. A bus 7 carries data, address, access mode and other control signals among the main memory 15, registers 16 and memory access controller 11. A receive clock pulse CLK2, which may be suppressed when necessary, sets the data sent in a data register (not shown) in a device which receives the data.
In a so-constructed buffer memory system, the CPU 12 sends the access mode on the bus 6 as a memory access mode and address to which data is to be accessed. When the addressed data is in the buffer memory 13, the data is output onto the bus 6 without suppressing the receive clock pulse CLK2, and the data is received by the CPU 12 in 1 memory cycle, i.e., 1 clock cycle. When the addressed data is not in the buffer memory 13, the buffer memory 13 activates the MISS-HIT signal. On receipt of the MISS-HIT signal through a miss-hit detector 19, the memory access controller 11 sends the clock suppress or a clock suppress request signal CLKSP/CLKSPRQ to the CPU 12 through the clock suppress signal generator 17 for clock suppression and makes an access to (i.e., reads) the main memory 15 instead, to read the addressed data therefrom. After outputting the data read onto the bus 6, the memory access controller 11 releases the clock suppression.
On receipt of the CLKSP/CLKSPRQ signal, the CPU 12 suppresses the receive clock pulse CLK2 so that the CPU 12 does not attempt to receive data on the bus 6 and, when the clock suppression is released and the CLKSP/CLKSPRQ signal is deactivated, receives the data from the bus 6 by not suppressing the receive clock pulse CLK2.
When the CPU 12 reads data from the registers 16 or main memory 15, clock suppression is required because the data read has to be transferred from the bus 7 to the bus 6. In this case, a clock suppress condition detector 18 detects a clock suppress condition based on the access mode to perform a clock suppression as for the above-described cache miss (or miss-hit) condition.
In a system with a buffer memory as described above, a particular device (e.g., the memory access controller 11 in the example) detects a clock suppress condition and generates the clock suppress or a clock suppress request signal (CLKSP/CLKSPRQ) for clock suppression for other devices (e.g., CPU 12).
FIG. 2 is a circuit showing the first related art, where data is received in 1 clock cycle.
The MISS-HIT signal from the buffer memory 13 is ORed with other clock suppress signals 21 by an OR gate G11 and input to the terminal J of a J-K flip-flop FF11 to be held there. The output of the OR gate G11 and that of the flip-flop FF11 are ORed by an OR gate G12 to output a clock suppress signal CLKSP to the CPU 12. When a suppression release signal is input to the terminal K of the flip-flop FF11, the clock suppress signal CLKSP is deactivated.
In the CPU 12, the signal CLKSP received is input through an invertor N2 to an AND gate G21, by which the system clock pulse CLK1 is gated to produce a receive clock pulse CLK2. In the memory access controller 11, too, the system clock pulse CLK1 is gated by an AND gate G13 to produce a receive clock pulse CLK2.
FIG. 3 is a timing chart showing the occurrence of a cache hit to the circuit of FIG. 2, i.e., a timing chart showing a case where no clock suppress condition occurs. The figure shows that the receive clock pulse CLK2 is not suppressed with the clock suppress signal CLKSP not activated (low) and the data read from the buffer memory 13 is received by the CPU 12 in 1 clock cycle.
FIG. 4 is a timing chart showing the occurrence of a clock suppress condition to the circuit of FIG. 2. A clock suppress signal CLKSP, which is generated from the time a clock suppress signal rises until a suppression release signal falls, suppresses the receive clock pulse CLK2 during two clock cycles. The CPU 12 receives the data on the bus 6 with the receive clock pulse CLK2 occurring after the clock suppression is released.
FIG. 5 is a circuit showing the second related art, i.e., a circuit for the case where two clock cycles are required for data to be received. The memory access controller 11 outputs a clock suppress request signal CLKSPRQ through the clock suppress signal generator 17. In the CPU 12, the clock suppress request signal CLKSPRQ is input to a D-type flip-flop FF21 to generate a clock suppress signal CLKSP after 1 clock cycle.
FIG. 6 is a timing chart showing the occurrence of a cache hit to the circuit of FIG. 5. The figure shows that the receive clock pulse CLK2 is not suppressed and the data on the bus 6 is received by the CPU 12 in 2 clock cycles.
FIG. 7 is a timing chart which shows occurrence of a clock suppress condition to the circuit of FIG. 5. The receive clock pulse CLK2 is suppressed in the clock cycles following the 1 clock cycle where a clock suppress signal occurs and restarts when the clock suppression is released to receive the data.
A clock suppress signal must be valid well before the leading edge of the clock pulse to be suppressed. As described above, however, since it takes a comparatively long time to determine a cache miss and since the MISS-HIT signal comes from outside of the memory access controller 11, the memory access controller 11 requires a longer time before detecting a cache miss compared with other clock suppress signals (See reference numeral 1 in FIG. 4).
Accordingly, as the clock suppress signal CLKSP resulting from a cache miss reaches the CPU 12 later, the receive clock pulse CLK2 fails to be suppressed (See a glitch 2 in FIG. 4), thus causing the CPU 12 to receive invalid data. The same is true of the circuit of FIG. 5. To avoid this, the period of the system clock pulse CLK1 must be longer.
According to the conventional clock control circuit as described above, since the system clock frequency had to be set low because of a particular clock suppress condition which takes time to be determined, such as a cache miss, a problem is that it reduces the processing speed and therefore, reduces the performance of the data processing system.